In an effort to produce high-performance and low-power chips, the semiconductor industry has initiated the exploration and manufacture of three-dimensional (3D) integrated circuits (ICs) based on die stacking and through-silicon-vias (TSVs). To manufacture a 3D IC, multiple dies are produced with their own active device and metal layers. Vertical TSVs are embedded in the silicon of the die wafer and connect to metal layers of the chip. The TSVs are typically in the form of a metal pillar that extends into the silicon substrate through the active device area. The TSVs may be located in or near the scribe lane, or may be in areas designated as not having an active device.
After fabricating each die's TSVs and active device and metal layers, the dies are thinned through grinding, exposing the TSVs through the bottom of the die. The thinned dies are bonded to one another in a vertical stack to produce a functional stacked IC (SIC). The TSVs connect each die to the dies immediately adjacent to it, thus playing the role of interconnects in the SICs.
As with any fabricated component, defects may occur during the manufacturing process of TSVs that can degrade product quality. Therefore, testing schemes are important in order to manufacture reliable chips.
TSV testing can be separated into two distinct categories: pre-bond testing and post-bond testing. Pre-bond testing is directed to detecting defects that are inherent in the manufacture of the TSV itself, such as impurities or voids, while post-bond testing is directed to detecting faults caused by thinning, alignment, and bonding.
There are a number of pre-bond defects that can impact chip functionality. These include incomplete metal filling (or microvoids) in the TSVs, which increase resistance and path delay; partial breaks in the TSV, which result in a resistive path; and complete breaks in the TSV, which result in an open path. In addition, impurities in the TSV may also increase resistance and interconnect delay; and pinhole defects can lead to a leakage path to the substrate, with a corresponding increase in the capacitance between the TSV and the substrate. Since methods to “unbond” die are yet to be realized, even one faulty die can cause the entire stacked IC to be discarded, including all the good dies in the stack.
FIGS. 1A and 1B illustrate a microvoid defect and a pinhole defect, respectively, of a TSV. Referring to FIGS. 1A and 1B, a TSV is disposed in the substrate and can take the form of a metal pillar. The TSV may be formed by etching the substrate to form a deep via or trench, depositing a barrier material in the deep via or trench, and then depositing the material forming the TSV. When depositing the material forming the TSV in the deep via or trench, a microvoid, as shown in FIG. 1A, may occur in the TSV. This microvoid increases the resistance of the TSV. The pinhole defect, as shown in FIG. 1B, may occur from uneven forming of the barrier material and causes leakage between the TSV and the substrate, increasing the TSV capacitance.
Although interest in 3D-SIC testing has surged in the past year and a number of test and design for test (DFT) solutions have been proposed, pre-bond TSV testing remains a major challenge.
In particular, pre-bond testing of TSVs continues to be difficult due, in part, to TSV pitch and density. Specifically, TSV dimensions are generally much smaller than the probe needles used by probe cards, which makes direct probing of single TSVs effectively unfeasible. For example, current probe technology using cantilever or vertical probes require a minimum pitch of 35 μm, but TSVs currently have diameters of only 5 μm and pitches of 10 μm or smaller, resulting in the probe contacting multiple TSVs at one time unless large probe pads are provided for the individual TSVs.
Furthermore, since TSVs are single-ended in the dies at a pre-bond stage, built-in self-test (BIST) techniques tend to suffer from limitations in terms of observability and the types of measurements that are feasible. In particular, current BIST approaches tend to not be able to detect all types of defects and often require careful calibration and tuning. In addition, current BIST approaches tend to add considerably to die-area cost because the additional test structures per TSV and/or complex routing for each TSV used in the current BIST approaches occupy a relatively large die area.
Moreover, since a chip can have many TSVs with densities of 10000/mm2 or more and the amount of on-die area used for test grows with the number of TSVs on the chip, many BIST methods do not scale well (particularly those that use large on-die analog elements such as resistors and capacitors).
However, because TSV yield has been recognized as a major concern for the semiconductor industry, it is important to screen defective dies through pre-bond testing prior to bonding and stacking.